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cy7c64013 cy7c64113 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-08001 rev. ** revised september 7, 2001 c66011 cy7c64013 cy7c64113 full-speed usb (12 mbps) function
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 2 of 48 table of contents 1.0 features ................................................................................................................. .................... 5 2.0 functional overview ...................................................................................................... ....... 6 3.0 pin configurations ....................................................................................................... .......... 8 4.0 product summary tables ................................................................................................... .9 4.1 pin assignments ......................................................................................................... .................. 9 4.2 i/o register summary ..................................................................................................... .............. 9 4.3 instruction set summary .................................................................................................. .......... 11 5.0 programming model ........................................................................................................ ..... 12 5.1 14-bit program counter (pc) .............................................................................................. ........ 12 5.1.1 program memory organization ............................................................................................ ............. 13 5.2 8-bit accumulator (a) .................................................................................................... .............. 13 5.3 8-bit temporary register (x) ............................................................................................. ......... 13 5.4 8-bit program stack pointer (psp) ........................................................................................ .... 14 5.4.1 data memory organization ............................................................................................... ................. 14 5.5 8-bit data stack pointer (dsp) ........................................................................................... ........ 14 5.6 address modes ............................................................................................................ ................ 15 5.6.1 data (immediate) ....................................................................................................... .......................... 15 5.6.2 direct ................................................................................................................. .................................. 15 5.6.3 indexed ................................................................................................................ ................................15 6.0 clocking ................................................................................................................. ................... 15 7.0 reset .................................................................................................................... ....................... 16 7.1 power-on reset (por) ..................................................................................................... ........... 16 7.2 watch dog reset (wdr) .................................................................................................... ......... 16 8.0 suspend mode ............................................................................................................. ............. 17 9.0 general-purpose i/o (gpio) ports ................................................................................... 17 9.1 gpio configuration port .................................................................................................. ........... 18 9.2 gpio interrupt enable ports .............................................................................................. ......... 19 10.0 dac port ................................................................................................................ .................. 20 10.1 dac isink registers ..................................................................................................... ............. 20 10.2 dac port interrupts ..................................................................................................... .............. 21 11.0 12-bit free-running timer ............................................................................................... .. 21 11.1 timer (lsb) ............................................................................................................. ................... 21 11.2 timer (msb) ............................................................................................................. ................... 21 12.0 i 2 c and hapi configuration register ......................................................................... 22 13.0 i 2 c compatible controller ............................................................................................. 23 14.0 hardware assisted parallel interface (hapi) ....................................................... 24 15.0 processor status and control register ............................................................... 25 16.0 interrupts .............................................................................................................. ................ 26 16.1 interrupt vectors ....................................................................................................... ................. 27 16.2 interrupt latency ....................................................................................................... ................ 28 16.3 usb bus reset interrupt ................................................................................................. ..........28 16.4 timer interrupt ......................................................................................................... .................. 29
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 3 of 48 16.5 usb endpoint interrupts ................................................................................................. ..........29 16.6 dac interrupt ........................................................................................................... .................. 29 16.7 gpio/hapi interrupt ..................................................................................................... ............. 29 16.8 i 2 c interrupt ................................................................................................................... ............. 30 17.0 usb overview ............................................................................................................ ............. 30 17.1 usb serial interface engine (sie) ....................................................................................... ..... 30 17.2 usb enumeration ......................................................................................................... ............. 31 17.3 usb upstream port status and control .................................................................................. 31 18.0 usb serial interface engine operation .................................................................... 32 18.1 usb device address ...................................................................................................... ........... 32 18.2 usb device endpoints .................................................................................................... .......... 32 18.3 usb control endpoint mode register ..................................................................................... 3 2 18.4 usb non-control endpoint mode registers ........................................................................... 33 18.5 usb endpoint counter registers .......................................................................................... .. 33 18.6 endpoint mode/count registers update and locking mechanism ...................................... 34 19.0 usb mode tables ......................................................................................................... ......... 36 20.0 sample schematic ......................................................................................................... ....... 40 21.0 absolute maximum ratings ............................................................................................. 41 22.0 electrical characteristics ........................................................................................... 41 23.0 switching characteristics ............................................................................................. 43 24.0 ordering information .................................................................................................... ... 46 25.0 package diagrams ........................................................................................................ ...... 46 list of figures figure 5-1. program memory space with interrupt vector table .................................................. 13 figure 6-1. clock oscillator on-chip circuit ................................................................................. .. 15 figure 7-1. watch dog reset (wdr) ............................................................................................ .... 16 figure 9-1. block diagram of a gpio pin ...................................................................................... .. 17 figure 9-2. port 0 data 0x00 (read/write) .................................................................................... ..... 18 figure 9-3. port 1 data 0x01 (read/write) .................................................................................... ..... 18 figure 9-4. port 2 data 0x02 (read/write) .................................................................................... ..... 18 figure 9-5. port 3 data 0x03 (read/write) .................................................................................... ..... 18 figure 9-6. gpio configuration register 0x08 (read/write) ........................................................... 19 figure 9-7. port 0 interrupt enable 0x04 (read/write) ..................................................................... 19 figure 9-8. port 1 interrupt enable 0x05 (read/write) ..................................................................... 19 figure 9-9. port 2 interrupt enable 0x06 (read/write) ..................................................................... 19 figure 9-10. port 3 interrupt enable 0x07 (read/write) ................................................................... 19 figure 10-1. block diagram of a dac pin ...................................................................................... .. 20 figure 10-2. dac port data 0x30 (read/write) ................................................................................. 20 figure 10-3. dac port isink 0x38 to 0x3f (write only) .................................................................... 20 figure 10-4. dac port interrupt enable 0x31 (write only) .............................................................. 21 figure 10-5. dac port interrupt polarity 0x32 (write only) ............................................................ 21 figure 11-1. timer register 0x24 (read only) ................................................................................. .21 figure 11-2. timer register 0x25 (read only) ................................................................................. .21 figure 11-3. timer block diagram ............................................................................................. ....... 22 figure 12-1. hapi/i 2 c configuration register 0x09 (read/write) ................................................... 22
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 4 of 48 figure 13-1. i 2 c data register 0x29 (separate read/write registers) ............................................. 23 figure 13-2. i 2 c status and control register 0x28 (read/write) .................................................... 23 figure 15-1. processor status and control register 0xff ............................................................ 25 figure 16-1. global interrupt enable register 0x20 (read/write) ................................................... 26 figure 16-2. usb endpoint interrupt enable register 0x21 (read/write) ...................................... 26 figure 16-3. interrupt controller functional diagram .................................................................... 27 figure 16-4. interrupt vector register 0x23 (read only) ................................................................. 28 figure 16-5. gpio interrupt structure ........................................................................................ ...... 29 figure 17-1. usb status and control register 0x1f (read/write) .................................................. 31 figure 18-1. usb device address register 0x10 (read/write) ....................................................... 32 figure 18-2. usb device endpoint zero mode register 0x12 (read/write) ................................... 32 figure 18-3. usb non-control device endpoint mode registers 0x14, 0x16, 0x42, 0x44, (read/write) .......................................................................................... ..... 33 figure 18-4. usb endpoint counter registers 0x11, 0x13, 0x15, 0x41, 0x43 (read/write) .......... 33 figure 18-5. token/data packet flow diagram ............................................................................... 35 figure 22-1. clock timing .................................................................................................... ............. 44 figure 22-2. usb data signal timing .......................................................................................... ..... 44 figure 22-3. hapi read by external interface from usb microcontroller .................................... 44 figure 22-4. hapi write by external device to usb microcontroller ............................................ 45 list of tables table 4-1. pin assignments ................................................................................................... ............. 9 table 4-2. i/o register summary .............................................................................................. .......... 9 table 4-3. instruction set summary ........................................................................................... ...... 11 table 9-1. port configurations ............................................................................................... .......... 18 table 12-1. hapi port configuration .......................................................................................... ...... 22 table 12-2. i 2 c port configuration ................................................................................................... 22 table 13-1. i 2 c status and control register bit definitions .......................................................... 23 table 14-1. port 2 pin and hapi configuration bit definitions ..................................................... 25 table 16-1. interrupt vector assignments ..................................................................................... .. 28 table 17-1. control bit definition for upstream port ..................................................................... 31 table 18-1. memory allocation for endpoints ................................................................................ 3 2 table 19-1. usb register mode encoding ...................................................................................... 3 6 table 19-2. decode table for table 19-3 : ?details of modes for differing traffic conditions? ... 37 table 19-3. details of modes for differing traffic conditions ....................................................... 38
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 5 of 48 1.0 features full-speed usb microcontroller 8-bit usb optimized microcontroller ? harvard architecture ? 6-mhz external clock source ? 12-mhz internal cpu clock ? 48-mhz internal clock internal memory ? 256 bytes of ram ? 8 kb of prom (cy7c64013, cy7c64113) integrated master/slave i 2 c compatible controller (100 khz) enabled through general-purpose i/o (gpio) pins hardware assisted parallel interface (hapi) for data transfer to external devices i/o ports ? three gpio ports (port 0 to 2) capable of sinking 7 ma per pin (typical) ? an additional gpio port (port 3) capable of sinking 12 ma per pin (typical) for high current requirements: leds ? higher current drive achievable by connecting multiple gpio pins together to drive a common output ? each gpio port can be configured as inputs with internal pull-ups or open drain outputs or traditional cmos outputs ? a digital to analog conversion (dac) port with programmable current sink outputs is available on the cy7c64113 devices ? maskable interrupts on all i/o pins 12-bit free-running timer with one microsecond clock ticks watch dog timer (wdt) internal power-on reset (por) usb specification compliance ? conforms to usb specification, version 1.1 ? conforms to usb hid specification, version 1.1 ? supports up to five user configured endpoints up to four 8-byte data endpoints up to two 32-byte data endpoints ? integrated usb transceivers improved output drivers to reduce emi operating voltage from 4.0v to 5.5v dc operating temperature from 0 to 70 degrees celsius ? cy7c64013 available in 28-pin soic and 28-pin pdip packages ? cy7c64113 available in 48-pin ssop packages industry-standard programmer support
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 6 of 48 2.0 functional overview the cy7c64013 and cy7c64113 are 8-bit one time programmable microcontrollers that are designed for full-speed usb applications. the instruction set has been optimized specifically for usb operations, although the microcontrollers can be used for a variety of non-usb embedded applications. the cy7c64013 features 19 gpio pins to support usb and other applications. the i/o pins are grouped into three ports (p0[7:0], p1[7:0], p3[7,2,0]) where each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional cmos outputs. there are 16 gpio pins (ports 0 and 1) which are rated at 7 ma typical sink current. port 3 pins are rated at 12 ma typical sink current, a current sufficient to drive leds. multiple gpio pins can be connected together to drive a single output for more drive current capacity. additionally, each gpio can be used to generate a gpio interrupt to the microcontroller. all of th e gpio interrupts share the same ? gpio ? interrupt vector. thirty-two gpio pins (p0[7:0], p1[7:0], p2[7:0], p3[7:0]) and four digital to analog conversion (dac) pins (p4[7,2:0]) are avai lable on the cy7c64113. every dac pin includes an integrated 14-k ? pull-up resistor. when a ? 1 ? is written to a dac i/o pin, the output current sink is disabled and the output pin is driven high by the internal pull-up resistor. when a ? 0 ? is written to a dac i/o pin, the internal pull-up resistor is disabled and the output pin provides the programmed amount of sink current. a dac i/o pin can be used as an input with an internal pull-up by writing a ? 1 ? to the pin. the sink current for each dac i/o pin can be individually programmed to one of 16 values using dedicated isink registers. dac bits p4[1:0] can be used as high-current outputs with a programmable sink current range of 3.2 to 16 ma (typical). dac bits p4[7,2] have a programmable current sink range of 0.2 to 1.0 ma (typical). multiple dac pins can be connected together to drive a single output that requires more sink current capacity. each i/o pin can be used to generate a dac interrupt to the microcon- troller. also, the interrupt polarity for each dac i/o pin is individually programmable. the microcontroller uses an external 6-mhz crystal and an internal oscillator to provide a reference to an internal pll-based clock generator. this technology allows the customer application to use an inexpensive 6-mhz fundamental crystal that reduces the clock-related noise emissions (emi). a pll clock generator provides the 6-, 12-, and 48-mhz clock signals for distribution within the microcontroller. the cy7c64013 and cy7c64113 have 8 kb of prom. these parts include power-on reset logic, a watch dog timer, and a 12-bit free-running timer. the power-on reset (por) logic detects when power is applied to the device, resets the logic to a known sta te, and begins executing instructions at prom address 0x0000. the watch dog timer is used to ensure the microcontroller recovers after a period of inactivity. the firmware may become inactive for a variety of reasons, including errors in the code or a hard ware failure such as waiting for an interrupt that never occurs. the microcontroller can communicate with external electronics through the gpio pins. an i 2 c compatible interface accommo- dates a 100-khz serial link with an external device. there is also a hardware assisted parallel interface (hapi) which can be used to transfer data to an external device. the free-running 12-bit timer clocked at 1 mhz provides two interrupt sources, 128- s and 1.024-ms. the timer can be used to measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is complete. the difference between the two readings indicates the duration of the event in microseconds. the upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. a read from the upper four bits a ctually reads data from the internal register, instead of the timer. this feature eliminates the need for firmware to try to compensate if the upper four bits increment immediately after the lower eight bits are read. the microcontroller supports 11 maskable interrupts in the vectored interrupt controller. interrupt sources include the usb bus reset interrupt, the 128- s (bit 6) and 1.024-ms (bit 9) outputs from the free-running timer, five usb endpoints, the dac port, the gpio ports, and the i 2 c compatible master mode interface. the timer bits cause an interrupt (if enabled) when the bit toggles from low ? 0 ? to high ? 1. ? the usb endpoints interrupt after the usb host has written data to the endpoint fifo or after the usb controller sends a packet to the usb host. the dac ports have an additional level of masking that allows the user to select whi ch dac inputs can cause a dac interrupt. the gpio ports also have a level of masking to select which gpio inputs can cause a gpio interrupt. for additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the dac port. input transition polarity can be programmed for each gpio port as part of the port configuration. the interrupt polar ity can be rising edge ( ? 0 ? to ? 1 ? ) or falling edge ( ? 1 ? to ? 0 ? ).
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 7 of 48 . logic block diagram interrupt controller prom 12-bit timer reset watch dog timer power-on sclk i 2 c gpio port 1 gpio port 0 p0[7:0] p1[2:0] p1[7:3] sdata 8-bit bus 6-mhz crystal ram usb sie usb transceiver d+[0] d ? [0] upstream usb port p3[2:0] dac port dac[0] dac[2] high current outputs cy7c64113 only 256 byte 8 kb clock 6 mhz 12-mhz 8-bit cpu *i 2 c compatible interface enabled by firmware through interface p3[7:3] additional outputs high current pll 12 mhz 48 mhz divider gpio/ port 2 p2[0,1,7] p2[3]; data_ready p2[4]; stb p2[5]; oe p2[6]; cs p2[2]; latch_empty hapi p2[1:0] or p1[1:0] cy7c64113 only port 3 gpio dac[7]
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 8 of 48 3.0 pin configurations 1 2 3 4 5 6 7 9 11 12 13 14 15 16 18 17 xtalin 10 8 19 20 31 30 29 33 32 35 34 37 36 39 38 41 40 43 42 45 44 46 48 47 21 22 23 24 25 27 26 28 v cc p1[1] p1[0] p1[2] p1[4] p1[6] p3[0] p3[2] v ref p1[3] p1[5] p1[7] p3[1] d+[0] d ? [0] p3[3] gnd p3[5] p3[7] p2[1] p2[3] gnd p2[5] p2[7] dac[7] p0[7] p0[5] p0[3] p0[1] dac[1] xtalout gnd p3[4] nc p3[6] p2[0] p2[2] gnd p2[4] p2[6] dac[0] v pp p0[0] p0[2] p0[4] p0[6] dac[2] cy7c64113 48-pin ssop cy7c64013 1 2 3 4 5 6 7 9 11 12 13 14 xtalin 10 8 15 17 16 19 18 21 20 23 22 25 24 26 28 27 v cc p1[1] p1[0] p1[2] p3[0] p3[2] gnd p2[2] v ref gnd p3[1] d+[0] d ? [0] p2[3] p2[5] p0[7] p0[5] p0[3] p0[1] p0[6] xtalout p2[4] p2[6] v pp p0[0] p0[2] p0[4] 28-pin soic cy7c64013 28-pin pdip top view 1 2 3 4 5 6 7 9 11 12 13 14 xtalin 10 8 15 17 16 19 18 21 20 23 22 25 24 26 28 27 v cc p1[0] p1[2] p3[0] p3[2] p2[2] gnd p2[4] v ref p1[1] gnd p3[1] d+[0] d ? [0] p2[3] p2[5] p0[7] p0[5] p0[3] p0[1] xtalout p2[6] v pp p0[0] p0[2] p0[4] p0[6]
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 9 of 48 4.0 product summary tables 4.1 pin assignments 4.2 i/o register summary i/o registers are accessed via the i/o read (iord) and i/o write (iowr, iowx) instructions. iord reads data from the selected port into the accumulator. iowr performs the reverse; it writes data from the accumulator to the selected port. indexed i/o wri te (iowx) adds the contents of x to the address in the instruction to form the port address and writes data from the accumulator t o the specified port. specifying address 0 (e.g., iowx 0h) means the i/o register is selected solely by the contents of x. all undefined registers are reserved. it is important not to write to reserved registers as this may cause an undefined operati on or increased current consumption during operation. when writing to registers with reserved bits, the reserved bits must be writ ten with ? 0. ? table 4-1. pin assignments name i/o 28-pin soic 28-pin pdip 48-pin ssop description d+[0], d ? [0] i/o 6, 7 7, 8 7, 8 upstream port, usb differential data. p0 i/o p0[7:0] 10, 14, 11, 15, 12, 16, 13, 17 p0[7:0] 11, 15, 12, 16, 13, 17, 14, 18 p0[7:0] 20, 26, 21, 27, 22, 28, 23, 29 gpio port 0 capable of sinking 7 ma (typical). p1 i/o p1[2:0] 25, 27, 26 p1[2:0] 26, 4, 27 p1[7:0] 6, 43, 5, 44, 4, 45, 47, 46 gpio port 1 capable of sinking 7 ma (typical). p2 i/o p2[6:2] 19, 9, 20, 8, 21 p2[6:2] 20, 10, 21, 9, 23 p2[7:0] 18, 32, 17, 33, 15, 35, 14, 36 gpio port 2 capable of sinking 7 ma (typical). hapi is also supported through p2[6:2]. p3 i/o p3[2:0] 23, 5, 24 p3[2:0] 24, 6, 25 p3[7:0] 13, 37, 12, 39, 10, 41, 7, 42 gpio port 3, capable of sinking 12 ma (typical). dac i/o dac[7,2:0] 19, 25, 24, 31 dac port with programmable current sink outputs. dac[1:0] offer a programmable range of 3.2 to 16 ma typical. dac[7,2] have a programmable sink current range of 0.2 to 1.0 ma typical. xtal in in 2 2 2 6-mhz crystal or external clock input. xtal out out 1 1 1 6-mhz crystal out. v pp in 18 19 30 programming voltage supply, tie to ground during nor- mal operation. v cc in 28 28 48 voltage supply. gnd in 4, 22 5, 22 11, 16, 34, 40 ground. v ref in 3 3 3 external 3.3v supply voltage for the differential data output buffers and the d+ pull-up. nc 38 no connect. table 4-2. i/o register summary register name i/o address read/write function page port 0 data 0x00 r/w gpio port 0 data 18 port 1 data 0x01 r/w gpio port 1 data 18 port 2 data 0x02 r/w gpio port 2 data 18 port 3 data 0x03 r/w gpio port 3 data 18 port 0 interrupt enable 0x04 w interrupt enable for pins in port 0 19 port 1 interrupt enable 0x05 w interrupt enable for pins in port 1 19 port 2 interrupt enable 0x06 w interrupt enable for pins in port 2 19 port 3 interrupt enable 0x07 w interrupt enable for pins in port 3 19
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 10 of 48 gpio configuration 0x08 r/w gpio port configurations 19 hapi and i 2 c configuration 0x09 r/w hapi width and i 2 c position configuration 22 usb device address a 0x10 r/w usb device address a 32 ep a0 counter register 0x11 r/w usb address a, endpoint 0 counter 33 ep a0 mode register 0x12 r/w usb address a, endpoint 0 configuration 32 ep a1 counter register 0x13 r/w usb address a, endpoint 1 counter 33 ep a1 mode register 0x14 r/w usb address a, endpoint 1 configuration 33 ep a2 counter register 0x15 r/w usb address a, endpoint 2 counter 33 ep a2 mode register 0x16 r/w usb address a, endpoint 2 configuration 33 usb status & control 0x1f r/w usb upstream port traffic status and control 31 global interrupt enable 0x20 r/w global interrupt enable 26 endpoint interrupt enable 0x21 r/w usb endpoint interrupt enables 26 interrupt vector 0x23 r pending interrupt vector read / clear 28 timer (lsb) 0x24 r lower 8 bits of free-running timer (1 mhz) 21 timer (msb) 0x25 r upper 4 bits of free-running timer 21 wdt clear 0x26 w watch dog timer clear 16 i 2 c control & status 0x28 r/w i 2 c status and control 23 i 2 c data 0x29 r/w i 2 c data 23 dac data 0x30 r/w dac data 20 dac interrupt enable 0x31 w interrupt enable for each dac pin 21 dac interrupt polarity 0x32 w interrupt polarity for each dac pin 21 dac isink 0x38-0x3f w input sink current control for each dac pin 20 reserved 0x40 reserved ep a3 counter register 0x41 r/w usb address a, endpoint 3 counter 33 ep a3 mode register 0x42 r/w usb address a, endpoint 3 configuration 32 ep a4 counter register 0x43 r/w usb address a, endpoint 4 counter 33 ep a4 mode register 0x44 r/w usb address a, endpoint 4 configuration 33 reserved 0x48 reserved reserved 0x49 reserved reserved 0x4a reserved reserved 0x4b reserved reserved 0x4c reserved reserved 0x4d reserved reserved 0x4e reserved reserved 0x4f reserved reserved 0x50 reserved reserved 0x51 reserved processor status & control 0xff r/w microprocessor status and control register 25 table 4-2. i/o register summary (continued) register name i/o address read/write function page
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 11 of 48 4.3 instruction set summary refer to the cyasm assembler user?s guide for more details. table 4-3. instruction set summary mnemonic operand opcode cycles mnemonic operand opcode cycles halt 00 7 nop 20 4 add a,expr data 01 4 inc a acc 21 4 add a,[expr] direct 02 6 inc x x 22 4 add a,[x+expr] index 03 7 inc [expr] direct 23 7 adc a,expr data 04 4 inc [x+expr] index 24 8 adc a,[expr] direct 05 6 dec a acc 25 4 adc a,[x+expr] index 06 7 dec x x 26 4 sub a,expr data 07 4 dec [expr] direct 27 7 sub a,[expr] direct 08 6 dec [x+expr] index 28 8 sub a,[x+expr] index 09 7 iord expr address 29 5 sbb a,expr data 0a 4 iowr expr address 2a 5 sbb a,[expr] direct 0b 6 pop a 2b 4 sbb a,[x+expr] index 0c 7 pop x 2c 4 or a,expr data 0d 4 push a 2d 5 or a,[expr] direct 0e 6 push x 2e 5 or a,[x+expr] index 0f 7 swap a,x 2f 5 and a,expr data 10 4 swap a,dsp 30 5 and a,[expr] direct 11 6 mov [expr],a direct 31 5 and a,[x+expr] index 12 7 mov [x+expr],a index 32 6 xor a,expr data 13 4 or [expr],a direct 33 7 xor a,[expr] direct 14 6 or [x+expr],a index 34 8 xor a,[x+expr] index 15 7 and [expr],a direct 35 7 cmp a,expr data 16 5 and [x+expr],a index 36 8 cmp a,[expr] direct 17 7 xor [expr],a direct 37 7 cmp a,[x+expr] index 18 8 xor [x+expr],a index 38 8 mov a,expr data 19 4 iowx [x+expr] index 39 6 mov a,[expr] direct 1a 5 cpl 3a 4 mov a,[x+expr] index 1b 6 asl 3b 4 mov x,expr data 1c 4 asr 3c 4 mov x,[expr] direct 1d 5 rlc 3d 4 reserved 1e rrc 3e 4 xpage 1f 4 ret 3f 8 mov a,x 40 4 di 70 4 mov x,a 41 4 ei 72 4 mov psp,a 60 4 reti 73 8 call addr 50 - 5f 10 jc addr c0-cf 5 jmp addr 80-8f 5 jnc addr d0-df 5 call addr 90-9f 10 jacc addr e0-ef 7 jz addr a0-af 5 index addr f0-ff 14 jnz addr b0-bf 5
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 12 of 48 5.0 programming model 5.1 14-bit program counter (pc) the 14-bit program counter (pc) allows access to up to 8 kb of prom available with the cy7c64x13 architecture. the top 32 bytes of the rom in the 8 kb part are reserved for testing purposes. the program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h. typically, this is a jump instruction to a reset handler that i nitializes the application (see interrupt vectors on page 27). the lower eight bits of the program counter are incremented as instructions are loaded and executed. the upper six bits of the program counter are incremented by executing an xpage instruction. as a result, the last instruction executed within a 256-byte ? page ? of sequential code should be an xpage instruction. the assembler directive ? xpageon ? causes the assembler to insert xpage instructions automatically. because instructions can be either one or two bytes long, the assembler may occasionally need to insert a nop followed by an xpage to execute correctly. the address of the next instruction to be executed, the carry flag, and the zero flag are saved as two bytes on the program sta ck during an interrupt acknowledge or a call instruction. the program counter, carry flag, and zero flag are restored from the program stack during a reti instruction. only the program counter is restored during a ret instruction. the program counter cannot be accessed directly by the firmware. the program stack can be examined by reading sram from location 0x00 and up.
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 13 of 48 5.1.1 program memory organization 5.2 8-bit accumulator (a) the accumulator is the general-purpose register for the microcontroller. 5.3 8-bit temporary register (x) the ? x ? register is available to the firmware for temporary storage of intermediate results. the microcontroller can perform indexed operations based on the value in x. refer to section 5.6.3 for additional information. after reset address 14-bit pc 0x0000 program execution begins here after a reset 0x0002 usb bus reset interrupt vector 0x0004 128- s timer interrupt vector 0x0006 1.024-ms timer interrupt vector 0x0008 usb address a endpoint 0 interrupt vector 0x000a usb address a endpoint 1 interrupt vector 0x000c usb address a endpoint 2 interrupt vector 0x000e usb address a endpoint 3 interrupt vector 0x0010 usb address a endpoint 4 interrupt vector 0x0012 reserved 0x0014 dac interrupt vector 0x0016 gpio interrupt vector 0x0018 i 2 c interrupt vector 0x001a program memory begins here 0x1fdf 8 kb (-32) prom ends here (cy7c64013, cy7c64113) figure 5-1. program memory space with interrupt vector table
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 14 of 48 5.4 8-bit program stack pointer (psp) during a reset, the program stack pointer (psp) is set to 0x00 and ? grows ? upward from this address. the psp may be set by firmware, using the mov psp,a instruction. the psp supports interrupt service under hardware control and call, ret, and reti instructions under firmware control. the psp is not readable by the firmware. during an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as two bytes of data memory. the first byte is stored in the memory addressed by the psp, then the psp is incremented. the second byte is stored in memory addressed by the psp, and the psp is incremented again. the overall effect is to store the program counter and flags on the program ? stack ? and increment the psp by two. the return from interrupt (reti) instruction decrements the psp, then restores the second byte from memory addressed by the psp. the psp is decremented again and the first byte is restored from memory addressed by the psp. after the program counter and flags have been restored from stack, the interrupts are enabled. the overall effect is to restore the program counter and f lags from the program stack, decrement the psp by two, and re-enable interrupts. the call subroutine (call) instruction stores the program counter and flags on the program stack and increments the psp by two. the return from subroutine (ret) instruction restores the program counter but not the flags from the program stack and decre- ments the psp by two. 5.4.1 data memory organization the cy7c64x13 microcontrollers provide 256 bytes of data ram. normally, the sram is partitioned into four areas: program stack, user variables, data stack, and usb endpoint fifos. the following is one example of where the program stack, data stack, and user variables areas could be located. 5.5 8-bit data stack pointer (dsp) the data stack pointer (dsp) supports push and pop instructions that use the data stack for temporary storage. a push instruction pre-decrements the dsp, then writes data to the memory location addressed by the dsp. a pop instruction reads data from the memory location addressed by the dsp, then post-increments the dsp. during a reset, the dsp is reset to 0x00. a push instruction when dsp equals 0x00 writes data at the top of the data ram (address 0xff). this writes data to the memory area reserved for usb endpoint fifos. therefore, the dsp should be indexed at an appropriate memory location that does not compromise the program stack, user-defined memory (variables), or the usb endpoint fifos. for usb applications, the firmware should set the dsp to an appropriate location to avoid a memory conflict with ram dedicated to usb fifos. the memory requirements for the usb endpoints are described in section 18.2. example assembly instructions to do this with two device addresses (fifos begin at 0xd8) are shown below: mov a,20h ; move 20 hex into accumulator (must be d8h or less) swap a,dsp ; swap accumulator value into dsp register notes: 1. refer to section 5.5 for a description of dsp. 2. endpoint sizes are fixed by the endpoint size bit (i/o register 0x1f, bit 7), see table 18-1 . after reset address 8-bit dsp 8-bit psp 0x00 program stack growth (move dsp [1] ) 8-bit dsp user selected data stack growth user variables usb fifo space for five endpoints [2] 0xff
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 15 of 48 5.6 address modes the cy7c64013 and cy7c64113 microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. 5.6.1 data (immediate) ? data ? address mode refers to a data operand that is actually a constant encoded in the instruction. as an example, consider the instruction that loads a with the constant 0xd8: mov a,0d8h this instruction requires two bytes of code where the first byte identifies the ? mov a ? instruction with a data operand as the second byte. the second byte of the instruction is the constant ? 0xd8. ? a constant may be referred to by name if a prior ? equ ? statement assigns the constant value to the name. for example, the following code is equivalent to the example shown above: dspinit: equ 0d8h mov a,dspinit 5.6.2 direct ? direct ? address mode is used when the data operand is a variable stored in sram. in that case, the one byte address of the variable is encoded in the instruction. as an example, consider an instruction that loads a with the contents of memory address location 0x10: mov a,[10h] normally, variable names are assigned to variable addresses using ? equ ? statements to improve the readability of the assembler source code. as an example, the following code is equivalent to the example shown above: buttons: equ 10h mov a,[buttons] 5.6.3 indexed ? indexed ? address mode allows the firmware to manipulate arrays of data stored in sram. the address of the data operand is the sum of a constant encoded in the instruction and the contents of the ? x ? register. normally, the constant is the ? base ? address of an array of data and the x register contains an index that indicates which element of the array is actually addressed: array: equ 10h mov x,3 mov a,[x+array] this would have the effect of loading a with the fourth element of the sram ? array ? that begins at address 0x10. the fourth element would be at address 0x13. 6.0 clocking figure 6-1. clock oscillator on-chip circuit the xtalin and xtalout are the clock pins to the microcontroller. the user can connect an external oscillator or a crystal to these pins. when using an external crystal, keep pcb traces between the chip leads and crystal as short as possible (less than 2 cm). a 6-mhz fundamental frequency parallel resonant crystal can be connected to these pins to provide a reference frequency for the internal pll. the two internal 30-pf load caps appear in series to the external crystal and would be equivalent to a 15 pf load. therefore, the crystal must have a required load capacitance of about 15 ? 18 pf. a ceramic resonator does not allow the microcontroller to meet the timing specifications of full speed usb and therefore a ceramic resonator is not recommended with these parts. an external 6-mhz clock can be applied to the xtalin pin if the xtalout pin is left open. grounding the xtalout pin when driving xtalin with an oscillator does not work because the internal clock is effectively shorted to ground. xtalout xtalin to internal pll 30 pf 30 pf (pin 1) (pin 2)
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 16 of 48 7.0 reset the cy7c64x13 supports two resets: power-on reset (por) and a watch dog reset (wdr). each of these resets causes: all registers to be restored to their default states, the usb device address to be set to 0, all interrupts to be disabled, the psp and data stack pointer (dsp) to be set to memory address 0x00. the occurrence of a reset is recorded in the processor status and control register, as described in section 15.0. bits 4 and 6 are used to record the occurrence of por and wdr, respectively. firmware can interrogate these bits to determine the cause of a reset. program execution starts at rom address 0x0000 after a reset. although this looks like interrupt vector 0, there is an importan t difference. reset processing does not push the program counter, carry flag, and zero flag onto program stack. the firmware reset handler should configure the hardware before the ? main ? loop of code. attempting to execute a ret or reti in the firmware reset handler causes unpredictable execution results. 7.1 power-on reset (por) when v cc is first applied to the chip, the power-on reset (por) signal is asserted and the cy7c64x13 enters a ? semi-suspend ? state. during the semi-suspend state, which is different from the suspend state defined in the usb specification, the oscillato r and all other blocks of the part are functional, except for the cpu. this semi-suspend time ensures that both a valid v cc level is reached and that the internal pll has time to stabilize before full operation begins. when the v cc has risen above approximately 2.5v, and the oscillator is stable, the por is deasserted and the on-chip timer starts counting. the first 1 ms of suspend time is not interruptible, and the semi-suspend state continues for an additional 95 ms unless the count is bypassed by a usb bus reset on the upstream port. the 95 ms provides time for v cc to stabilize at a valid operating voltage before the chip executes code. if a usb bus reset occurs on the upstream port during the 95-ms semi-suspend time, the semi-suspend state is aborted and program execution begins immediately from address 0x0000. in this case, the bus reset interrupt is pending but not serviced until firmware sets the usb bus reset interrupt enable bit (bit 0 of register 0x20) and enables interrupts with the ei command. the por signal is asserted whenever v cc drops below approximately 2.5v, and remains asserted until v cc rises above this level again. behavior is the same as described above. 7.2 watch dog reset (wdr) the watch dog timer reset (wdr) occurs when the internal watch dog timer rolls over. writing any value to the write-only watch dog restart register at address 0x26 clears the timer. the timer rolls over and wdr occurs if it is not cleared within t watch (8 ms minimum) of the last clear. bit 6 of the processor status and control register is set to record this event (the register contents are set to 010x0001 by the wdr). a watch dog timer reset lasts for 2 ms, after which the microcontroller begins execution at rom address 0x0000. figure 7-1. watch dog reset (wdr) the usb transmitter is disabled by a watch dog reset because the usb device address register is cleared (see section 18.1). otherwise, the usb controller would respond to all address 0 transactions. it is possible for the wdr bit of the processor status and control register (0xff) to be set following a por event. the wdr bit should be ignored if the firmware interrogates the processor status and control register for a set condition on the wdr bit and if the por (bit 3 of register 0xff) bit is set. last write to watch dog timer register no write to wdt register, so wdr goes high execution begins at reset vector 0x0000 t watch 2 ms
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 17 of 48 8.0 suspend mode the cy7c64x13 can be placed into a low-power state by setting the suspend bit of the processor status and control register. all logic blocks in the device are turned off except the gpio interrupt logic and the usb receiver. the clock oscillator and pl l, as well as the free-running and watch dog timers, are shut down. only the occurrence of an enabled gpio interrupt or non-idle bus activity at a usb upstream or downstream port wakes the part out of suspend. the run bit in the processor status and control register must be set to resume a part out of suspend. the clock oscillator restarts immediately after exiting suspend mode. the microcontroller returns to a fully functional state 1 ms after the oscillator is stable. the microcontroller executes the instruction following the i/o write that placed the device int o suspend mode before servicing any interrupt requests. the gpio interrupt allows the controller to wake-up periodically and poll system components while maintaining a very low averag e power consumption. to achieve the lowest possible current during suspend mode, all i/o should be held at v cc or gnd. this also applies to internal port pins that may not be bonded in a particular package. typical code for entering suspend is shown below: ... ; all gpio set to low-power state (no floating pins) ... ; enable gpio interrupts if desired for wake-up mov a, 09h ; set suspend and run bits iowr ffh ; write to status and control register - enter suspend, wait for usb activity (or gpio interrupt) nop ; this executes before any isr ... ; remaining code for exiting suspend routine 9.0 general-purpose i/o (gpio) ports there are up to 32 gpio pins (p0[7:0], p1[7:0], p2[7:0], and p3[7:0]) for the hardware interface. the number of gpio pins changes based on the package type of the chip. each port can be configured as inputs with internal pull-ups, open drain outputs , or traditional cmos outputs. port 3 offers a higher current drive, with typical current sink capability of 12 ma. the data for each gpio port is accessible through the data registers. port data registers are shown in figure 9-2 through figure 9-5 , and are set to 1 on reset. figure 9-1. block diagram of a gpio pin gpio v cc 14 k ? gpio cfg mode 2-bits data out latch internal data bus port read port write interrupt enable control control interrupt controller q1 q3* q2 *port 0,1,2: low i sink port 3: high i sink data interrupt latch oe reg_bit strb data in latch (latch is transparent except in hapi mode) pin
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 18 of 48 special care should be taken with any unused gpio data bits. an unused gpio data bit, either a pin on the chip or a port bit th at is not bonded on a particular package, must not be left floating when the device enters the suspend state. if a gpio data bit i s left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the usb specifications. if a ? 1 ? is written to the unused data bit and the port is configured with open drain outputs, the unused data bit remains in an indeterminate state. therefore, if an unused port bit is programmed in open-drain mode, it must be written with a ? 0. ? notice that the cy7c64013 part always requires that the data bits p1[7:3], p2[7,1,0], and p3[7:3] be written with a ? 0. ? in normal non-hapi mode, reads from a gpio port always return the present state of the voltage at the pin, independent of the settings in the port data registers. if hapi mode is activated for a port, reads of that port return latched data as controlled by the hapi signals (see section 14.0). during reset, all of the gpio pins are set to a high-impedance input state ( ? 1 ? in open drain mode). writing a ? 0 ? to a gpio pin drives the pin low. in this state, a ? 0 ? is always read on that gpio pin unless an external source overdrives the internal pull-down device. 9.1 gpio configuration port every gpio port can be programmed as inputs with internal pull-ups, open drain outputs, and traditional cmos outputs. in addition, the interrupt polarity for each port can be programmed. with positive interrupt polarity, a rising edge ( ? 0 ? to ? 1 ? ) on an input pin causes an interrupt. with negative polarity, a falling edge ( ? 1 ? to ? 0 ? ) on an input pin causes an interrupt. as shown in the table below, when a gpio port is configured with cmos outputs, interrupts from that port are disabled. the gpio configuration port register provides two bits per port to program these features. the possible port configurations are detailed in table 9-1 : in ? resistive ? mode, a 14-k ? pull-up resistor is conditionally enabled for all pins of a gpio port. an i/o pin is driven high through a 14-k ? pull-up resistor when a ? 1 ? has been written to the pin. the output pin is driven low with the pull-up disabled when a ? 0 ? has been written to the pin. an i/o pin that has been written as a ? 1 ? can be used as an input pin with the integrated 14-k ? pull-up resistor. resistive mode selects a negative (falling edge) interrupt polarity on all pins that have the gpio interrupt enabled. 7 6 5 4 3 2 1 0 p0[7] p0[6] p0[5] p0[4] p0[3] p0[2] p0[1] p0[0] figure 9-2. port 0 data 0x00 (read/write) 7 6 5 4 3 2 1 0 p1[7] p1[6] p1[5] p1[4] p1[3] p1[2] p1[1] p1[0] figure 9-3. port 1 data 0x01 (read/write) 7 6 5 4 3 2 1 0 p2[7] p2[6] p2[5] p2[4] p2[3] p2[2] p2[1] p2[0] figure 9-4. port 2 data 0x02 (read/write) 7 6 5 4 3 2 1 0 p3[7] (see text) p3[6] p3[5] p3[4] p3[3] p3[2] p3[1] p3[0] figure 9-5. port 3 data 0x03 (read/write) table 9-1. port configurations port configuration bits pin interrupt bit driver mode interrupt polarity 11 0 resistive disabled 1resistive ? 10 0 cmos output disabled 1 open drain disabled 01 0 open drain disabled 1 open drain ? 00 (reset state) 0 open drain disabled (default condition) 1 open drain +
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 19 of 48 in ? cmos ? mode, all pins of the gpio port are outputs that are actively driven. a cmos port is not a possible source for interrupts. in ? open drain ? mode, the internal pull-up resistor and cmos driver (high) are both disabled. an open drain i/o pin that has been written as a ? 1 ? can be used as an input or an open drain output. an i/o pin that has been written as a ? 0 ? drives the output low. the interrupt polarity for an open drain gpio port can be selected as positive (rising edge) or negative (falling edge). during reset, all of the bits in the gpio configuration register are written with ? 0 ? to select open drain output for all gpio ports as the default configuration. 9.2 gpio interrupt enable ports each gpio pin can be individually enabled or disabled as an interrupt source. the port 0 ? 3 interrupt enable registers provide this feature with an interrupt enable bit for each gpio pin. when hapi mode (discussed in section 14.0) is enabled the gpio interrupts are blocked, including ports not used by hapi, so gpio pins cannot be used as interrupt sources. during a reset, gpio interrupts are disabled by clearing all of the gpio interrupt enable ports. writing a ? 1 ? to a gpio interrupt enable bit enables gpio interrupts from the corresponding input pin. all gpio pins share a common interrupt, as discussed in section 16.7. 7 6 5 4 3 2 1 0 port 3 config bit 1 port 3 config bit 0 port 2 config bit 1 port 2 config bit 0 port 1 config bit 1 port 1 config bit 0 port 0 config bit 1 port 0 config bit 0 figure 9-6. gpio configuration register 0x08 (read/write) 7 6 5 4 3 2 1 0 p0[7] p0[6] p0[5] p0[4] p0[3] p0[2] p0[1] p0[0] figure 9-7. port 0 interrupt enable 0x04 (write only) 7 6 5 4 3 2 1 0 p1[7] p1[6] p1[5] p1[4] p1[3] p1[2] p1[1] p1[0] figure 9-8. port 1 interrupt enable 0x05 (write only) 7 6 5 4 3 2 1 0 p2[7] p2[6] p2[5] p2[4] p2[3] p2[2] p2[1] p2[0] figure 9-9. port 2 interrupt enable 0x06 (write only) 7 6 5 4 3 2 1 0 reserved - set to zero p3[6] p3[5] p3[4] p3[3] p3[2] p3[1] p3[0] figure 9-10. port 3 interrupt enable 0x07 (write only)
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 20 of 48 10.0 dac port the cy7c64113 features a digital to analog conversion (dac) port which has programmable current sink on each i/o pin. writing a ? 1 ? to a dac i/o pin disables the output current sink (isink dac) and drives the i/o pin high through an integrated 14-k ? resistor. when a ? 0 ? is written to a dac i/o pin, the isink dac is enabled and the pull-up resistor is disabled. this causes the isink dac to sink current to drive the output low. the amount of sink current for the dac i/o pin is programmable over 16 values based on the contents of the dac isink register for that output pin. dac[1:0] are high-current outputs that are programmable from 3.2 ma to 16 ma (typical). dac[7:2] are low-current outputs, programmable from 0.2 ma to 1.0 ma (typical). when the suspend bit in processor status and control register (0xff) is set, the isink dac block of the dac circuitry is disabl ed. special care should be taken when the cy7c64x13 device is placed in the suspend mode. the dac port data register(0x30) should normally be loaded with all ? 1 ? s (0xff) before setting the suspend bit. if any of the dac bits are set to ? 0 ? when the device is suspended, that dac input will float. the floating pin could result in excessive current consumption by the device, unless a n external load places the pin in a deterministic state. when a dac i/o bit is written as a ? 1 ? , the i/o pin is an output pulled high through the 14-k ? resistor or an input with an internal 14-k ? pull-up resistor. all dac port data bits are set to ? 1 ? during reset. 10.1 dac isink registers each dac i/o pin has an associated dac isink register to program the output sink current when the output is driven low. the first isink register (0x38) controls the current for dac[0], the second (0x39) for dac[1], and so on until the isink register a t 0x3f controls the current to dac[7]. writing all ? 0 ? s to the isink register causes 1/5 of the max. current to flow through the dac i/o pin. writing all ? 1 ? s to the isink register provides the maximum current flow through the pin. the other 14 states of the dac sink current are evenly spaced between these two values. figure 10-1. block diagram of a dac pin low current outputs 0.2 ma to 1.0 ma typical high current outputs 3.2 ma to 16 ma typical 7 6 5 4 3 2 1 0 dac[7] dac[6] dac[5] dac[4] dac[3] dac[2] dac[1] dac[0] figure 10-2. dac port data 0x30 (read/write) isink value 7 6 5 4 3 2 1 0 reserved reserved reserved reserved isink[3] isink[2] isink[1] isink[0] figure 10-3. dac port isink 0x38 to 0x3f (write only) v cc 14 k ? data out latch internal data bus dac read dac write interrupt enable interrupt logic to interrupt controller q1 internal buffer interrupt polarity isink dac isink register 4 bits dac i/o pin suspend (bit 3 of register 0xff)
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 21 of 48 10.2 dac port interrupts a dac port interrupt can be enabled/disabled for each pin individually. the dac port interrupt enable register provides this feature with an interrupt enable bit for each dac i/o pin. writing a ? 1 ? to a bit in this register enables interrupts from the corre- sponding bit position. writing a ? 0 ? to a bit in the dac port interrupt enable register disables interrupts from the corresponding bit position. all of the dac port interrupt enable register bits are cleared to ? 0 ? during a reset. all dac pins share a common interrupt, as explained in section 16.6. as an additional benefit, the interrupt polarity for each dac pin is programmable with the dac port interrupt polarity register . writing a ? 0 ? to a bit selects negative polarity (falling edge) that causes an interrupt (if enabled) if a falling edge transition occurs on the corresponding input pin. writing a ? 1 ? to a bit in this register selects positive polarity (rising edge) that causes an interrupt (if enabled) if a rising edge transition occurs on the corresponding input pin. all of the dac port interrupt polarity register bits are cleared during a reset. 11.0 12-bit free-running timer the 12-bit timer provides two interrupts (128- s and 1.024-ms) and allows the firmware to directly time events that are up to 4 ms in duration. the lower 8 bits of the timer can be read directly by the firmware. reading the lower 8 bits latches the upper 4 bits into a temporary register. when the firmware reads the upper 4 bits of the timer, it is accessing the count stored in the temporary register. the effect of this logic is to ensure a stable 12-bit timer value can be read, even when the two reads are separated in time. 11.1 timer (lsb) 11.2 timer (msb) 7 6 5 4 3 2 1 0 dac[7] dac[6] dac[5] dac[4] dac[3] dac[2] dac[1] dac[0] figure 10-4. dac port interrupt enable 0x31 (write only) 7 6 5 4 3 2 1 0 dac[7] dac[6] dac[5] dac[4] dac[3] dac[2] dac[1] dac[0] figure 10-5. dac port interrupt polarity 0x32 (write only) 7 6 5 4 3 2 1 0 timer bit 7 timer bit 6 timer bit 5 timer bit 4 timer bit 3 timer bit 2 timer bit 1 timer bit 0 figure 11-1. timer register 0x24 (read only) 7 6 5 4 3 2 1 0 reserved reserved reserved reserved timer bit 11 timer bit 10 timer bit 9 timer bit 8 figure 11-2. timer register 0x25 (read only)
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 22 of 48 12.0 i 2 c and hapi configuration register internal hardware supports communication with external devices through two interfaces: a two-wire i 2 c compatible interface, and a hapi for 1, 2, or 3 byte transfers. the i 2 c compatible interface and hapi functions, discussed in detail in sections 13.0 and 14.0, share a common configuration register (see figure 12-1 ). all bits of this register are cleared on reset. bits [7,1:0] of the hapi/i 2 c configuration register control the pin out configuration of the hapi and i 2 c compatible interfaces. bits [5:2] are used in hapi mode only, and are described in section 14.0. table 12-1 shows the hapi port configurations, and table 12-2 shows i 2 c pin location configuration options. these i 2 c compatible options exist due to pin limitations in certain packages, and to allow simultaneous hapi and i 2 c compatible operation. hapi operation is enabled whenever either hapi port width bit (bit 1 or 0) is non-zero. this affects gpio operation as describe d in section 14.0. i 2 c compatible blocks must be separately enabled as described in section 13.0. figure 11-3. timer block diagram 7 6 5 4 3 2 1 0 r/w r/w r/w r r r/w r/w i 2 c position reserved lempty polarity drdy polarity latch empty data ready hapi port width bit 1 hapi port width bit 0 figure 12-1. hapi/i 2 c configuration register 0x09 (read/write) table 12-1. hapi port configuration port width bits[1:0] hapi port width 11 24 bits: p3[7:0], p1[7:0], p0[7:0] 10 16 bits: p1[7:0], p0[7:0] 01 8 bits: p0[7:0] 00 no hapi interface table 12-2. i 2 c port configuration i 2 c position bit[7] port width bit[1] i 2 c position x1i 2 c on p2[1:0], 0:scl, 1:sda 00i 2 c on p1[1:0], 0:scl, 1:sda 10i 2 c on p2[1:0], 0:scl, 1:sda 10 9 7 85 6432 1-mhz clock 1.024-ms interrupt 128- s interrupt to timer register 8 1 0 11 l1 l0 l2 l3 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 23 of 48 13.0 i 2 c compatible controller the i 2 c compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and multi-master modes of operation. the i 2 c compatible block functions by handling the low-level signaling in hardware, and issuing interrupts as needed to allow firmware to take appropriate action during transactions. while waiting for firmware response, the hardware keeps the i 2 c compatible bus idle if necessary. the i 2 c compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a stop bit is detected by the slave when in receive mode, or when arbitration is lost. details of the interrupt responses are giv en in section 16.8 . the i 2 c compatible interface consists of two registers, an i 2 c data register ( figure 13-1 ) and an i 2 c status and control register ( figure 13-2 ). the data register is implemented as separate read and write registers. generally, the i 2 c status and control register should only be monitored after the i 2 c interrupt, as all bits are valid at that time. polling this register at other times could read misleading bit status if a transaction is underway. the i 2 c scl clock is connected to bit 0 of gpio port 1 or gpio port 2, and the i 2 c sda data is connected to bit 1 of gpio port 1 or gpio port 2. refer to section 12.0 for the bit definitions and functionality of the hapi/i 2 c configuration register, which is used to set the locations of the configurable i 2 c compatible pins. once the i 2 c compatible functionality is enabled by setting bit 0 of the i 2 c status & control register, the two lsb bits ([1:0]) of the corresponding gpio port are placed in open drain mode, regardless of the settings of the gpio configuration register.the electrical characteristics of the i 2 c compatible interface is the same as that of gpio ports 1 and 2. note that the i ol (max) is 2 ma @ v ol = 2.0 v for ports 1 and 2. all control of the i 2 c clock and data lines is performed by the i 2 c compatible block. the i 2 c status and control register bits are defined in table 13-1 , with a more detailed description following. 7 6 5 4 3 2 1 0 i 2 c data 7 i 2 c data 6 i 2 c data 5 i 2 c data 4 i 2 c data 3 i 2 c data 2 i 2 c data 1 i 2 c data 0 figure 13-1. i 2 c data register 0x29 (separate read/write registers) 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w mstr mode continue/ busy xmit mode ack addr arb lost/ restart received stop i 2 c enable figure 13-2. i 2 c status and control register 0x28 (read/write) table 13-1. i 2 c status and control register bit definitions bit name description 0i 2 c enable write to 1 to enable i 2 c compatible function. when cleared, i 2 c compatible gpio pins operate normally. 1 received stop reads 1 only in slave receive mode, when i 2 c stop bit detected (unless firmware did not ack the last transaction). 2 arb lost/restart reads 1 to indicate master has lost arbitration. reads 0 otherwise. write to 1 in master mode to perform a restart sequence (also set continue bit). 3 addr reads 1 during first byte after start/restart in slave mode, or if master loses arbitration. reads 0 otherwise. this bit should always be written as 0. 4 ack in receive mode, write 1 to generate ack, 0 for no ack. in transmit mode, reads 1 if ack was received, 0 if no ack received. 5 xmit mode write to 1 for transmit mode, 0 for receive mode. 6 continue / busy write 1 to indicate ready for next transaction. reads 1 when i 2 c compatible block is busy with a transaction, 0 when transaction is complete. 7 mstr mode write to 1 for master mode, 0 for slave mode. this bit is cleared if master loses arbitration. clearing from 1 to 0 generates stop bit.
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 24 of 48 mstr mode: setting this bit causes the i 2 c compatible block to initiate a master mode transaction by sending a start bit and transmitting the first data byte from the data register (this typically holds the target address and r/w bit). subsequent bytes are initiated by setting the continue bit, as described below. in master mode, the i 2 c compatible block generates the clock (sck), and drives the data line as required depending on transmit or receive state. the i 2 c compatible block performs any required arbitration and clock synchronization. the loss of arbitration results in the clearing of this bit, the setting of the arb lost bit, and the generation of an interrupt to the microcontroller . if the chip is the target of an external master that wins arbitration, then the interrupt is held off until the transaction from the e xternal master is completed. when mstr mode is cleared from 1 to 0 by a firmware write, an i 2 c stop bit is generated. continue / busy: this bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin. in other words, the bit has responded to an interrupt request and has completed the required update or read of the data registe r. during a read this bit indicates if the hardware is busy and is locking out additional writes to the i 2 c status and control register. this locking allows the hardware to complete certain operations that may require an extended period of time. following an i 2 c interrupt, the i 2 c compatible block does not return to the busy state until firmware sets the continue bit. this allows the firmware to make one control register write without the need to check the busy bit. xmit mode: this bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. clear this bit for receive mode. firmware generally determines the value of this bit from the r/w bit associated with the i 2 c address packet. the xmit mode bit state is ignored when initially writing the mstr mode or the restart bits, as these cases always cause transm it mode for the first byte. ack: this bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ack signal on the i 2 c compatible bus. writing a 1 to this bit generates an ack (sda low) on the i 2 c compatible bus at the ack bit time. during transmits (xmit mode=1), this bit should be cleared. addr: this bit is set by the i 2 c compatible block during the first byte of a slave receive transaction, after an i 2 c start or restart. the addr bit is cleared when the firmware sets the continue bit. this bit allows the firmware to recognize when the master has lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred. arb lost/restart: this bit is valid as a status bit (arb lost) after master mode transactions. in master mode, set this bit (along with the continue and mstr mode bits) to perform an i 2 c restart sequence. the i 2 c target address for the restart must be written to the data register before setting the continue bit. to prevent false arb lost signals, the restart bit is cleared by hardware during the restart sequence. receive stop: this bit is set when the slave is in receive mode and detects a stop bit on the bus. the receive stop bit is not set if the firmware terminates the i 2 c transaction by not acknowledging the previous byte transmitted on the i 2 c compatible bus, e.g., in receive mode if firmware sets the continue bit and clears the ack bit. i 2 c enable: set this bit to override gpio definition with i 2 c compatible function on the two i 2 c compatible pins. when this bit is cleared, these pins are free to function as gpios. in i 2 c compatible mode, the two pins operate in open drain mode, independent of the gpio configuration setting. 14.0 hardware assisted parallel interface (hapi) the cy7c64x13 processor provides a hardware assisted parallel interface for bus widths of 8, 16, or 24 bits, to accommodate data transfer with an external microcontroller or similar device. control bits for selecting the byte width are in the hapi/i 2 c configuration register ( figure 12-1 ), bits 1 and 0. signals are provided on port 2 to control the hapi interface. table 14-1 describes these signals and the hapi control bits in the hapi/i 2 c configuration register. enabling hapi causes the gpio setting in the gpio configuration register (0x08) to be overridden. the port 2 output pins are in cmos output mode and port 2 input pins are in input mode (open drain mode with q3 off in figure 9-1 ).
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 25 of 48 hapi read by external device from cy7c64x13: in this case (see figure 23-3 ), firmware writes data to the gpio ports. if 16-bit or 24-bit transfers are being made, port 0 should be written last, since writes to port 0 asserts the data ready bit and the dreadypin to signal the external device that data is available. the external device then drives the oe and cs pins active (low), which causes the hapi data to be output on the port pins. when oe is returned high (inactive), the hapi/gpio interrupt is generated. at that point, firmware can reload the hapi latches for the next output, again writing port 0 last. the data ready bit reads the opposite state from the external dreadypin on pin p2[3]. if the drdy polarity bit is 0, dreadypin is active high, and the data ready bit is active low. hapi write by external device to cy7c64x13: in this case (see figure 23-4 ), the external device drives the stb and cs pins active (low) when it drives new data onto the port pins. when this happens, the internal latches become full which causes the latch empty bit to be deasserted. when stb is returned high (inactive), the hapi/gpio interrupt is generated. firmware then reads the parallel ports to empty the hapi latches. if 16-bit or 24-bit transfers are being made, port 0 should be read last be cause reads from port 0 assert the latch empty bit and the latemptypin to signal the external device for more data. the latch empty bit reads the opposite state from the external latemptypin on pin p2[2]. if the lempty polarity bit is 0, latemptypin is active high, and the latch empty bit is active low. 15.0 processor status and control register the run bit, bit 0, is manipulated by the halt instruction. when halt is executed, all the bits of the processor status and con trol register are cleared to 0. since the run bit is cleared, the processor stops at the end of the current instruction. the process or remains halted until an appropriate reset occurs (power-on or watch dog). this bit should normally be written as a ? 1. ? bit 1 is reserved and must be written as a zero. the interrupt enable sense (bit 2) shows whether interrupts are enabled or disabled. firmware has no direct control over this b it as writing a zero or one to this bit position has no effect on interrupts. a ? 0 ? indicates that interrupts are masked off and a ? 1 ? indicates that the interrupts are enabled. this bit is further gated with the bit settings of the global interrupt enable regis ter (0x20) and usb end point interrupt enable register (0x21). instructions di, ei, and reti manipulate the state of this bit. writing a ? 1 ? to the suspend bit (bit 3) halts the processor and causes the microcontroller to enter the suspend mode that significantly reduces power consumption. a pending, enabled interrupt or usb bus activity causes the device to come out of suspend. after coming out of suspend, the device resumes firmware execution at the instruction following the iowr which put the part into suspend. an iowr attempting to put the part into suspend is ignored if non-idle usb bus activity is present. see section 8.0 for more details on suspend mode operation. table 14-1. port 2 pin and hapi configuration bit definitions pin name direction description (port 2 pin) p2[2] latemptypin out ready for more input data from external interface. p2[3] dreadypin out output data ready for external interface. p2[4] stb in strobe signal for latching incoming data. p2[5] oe in output enable, causes chip to output data. p2[6] cs in chip select (gates stb and oe ). bit name r/w description (hapi/i 2 c configuration register) 2 data ready r asserted after firmware writes data to port 0, until oe driven low. 3 latch empty r asserted after firmware reads data from port 0, until stb driven low. 4 drdy polarity r/w determines polarity of data ready bit and dreadypin: if 0, data ready is active low, dreadypin is active high. if 1, data ready is active high, dreadypin is active low. 5 lempty polarity r/w determines polarity of latch empty bit and latemptypin: if 0, latch empty is active low, latemptypin is active high. if 1, latch empty is active high, latemptypin is active low. 7 6 5 4 3 2 1 0 r r/w r/w r/w r/w r r/w irq pending watch dog reset usb bus re- set interrupt power-on reset suspend interrupt enable sense reserved run figure 15-1. processor status and control register 0xff
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 26 of 48 the power-on reset (bit 4) is set to ? 1 ? during a power-on reset. the firmware can check bits 4 and 6 in the reset handler to determine whether a reset was caused by a power-on condition or a watch dog timeout. note that a por event may be followed by a watch dog reset before firmware begins executing, as explained below. the usb bus reset interrupt (bit 5) occurs when a usb bus reset is received on the upstream port. the usb bus reset is a single-ended zero (se0) that lasts from 12 to 16 s. an se0 is defined as the condition in which both the d+ line and the d ? line are low at the same time. when the sie detects that this se0 condition is removed, the usb bus reset interrupt bit is set in the processor status and control register and a usb bus reset interrupt is generated. the watch dog reset (bit 6) is set during a reset initiated by the watch dog timer. this indicates the watch dog timer went for more than t watch (8 ms minimum) between watch dog clears. this can occur with a por event, as noted below. the irq pending (bit 7), when set, indicates that one or more of the interrupts has been recognized as active. an interrupt rem ains pending until its interrupt enable bit is set (registers 0x20 or 0x21) and interrupts are globally enabled. at that point, the internal interrupt handling sequence clears this bit until another interrupt is detected as pending. during power-up, the processor status and control register is set to 00010001, which indicates a por (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). during the 96 ms suspend at start-up (explained in section 7.1), a watch dog reset also occurs unless this suspend is aborted by an upstream se0 before 8 ms. if a wdr occurs during the power-up suspend interval, firmware reads 01010001 from the status and control register after power-up. normally, the por bit should be cleared so a subsequent wdr can be clearly identified. if an upstream bus reset is received before firmware examines this register, the bus reset bit may also be set. during a watch dog reset, the processor status and control register is set to 01xx0001, which indicates a watch dog reset (bit 6 set) has occurred and no interrupts are pending (bit 7 clear). the watch dog reset does not effect the state of the por and the bus reset interrupt bits. 16.0 interrupts interrupts are generated by the gpio/dac pins, the internal timers, i 2 c compatible interface or hapi operation, or on various usb traffic conditions. all interrupts are maskable by the global interrupt enable register and the usb end point interrupt ena ble register. writing a ? 1 ? to a bit position enables the interrupt associated with that bit position. during a reset, the contents the global interrupt enable register and usb end point interrupt enable register are cleared, effectively disabling all interrupts. the interrupt controller contains a separate flip-flop for each interrupt. see figure 16-3 for the logic block diagram of the interrupt controller. when an interrupt is generated, it is first registered as a pending interrupt. it stays pending until it is service d or a reset occurs. a pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enab le registers. the highest priority interrupt request is serviced following the completion of the currently executing instruction. when servicing an interrupt, the hardware first disables all interrupts by clearing the global interrupt enable bit in the cpu (the state of this bit can be read at bit 2 of the processor status and control register). second, the flip-flop of the current inte rrupt is cleared. this is followed by an automatic call instruction to the rom address associated with the interrupt being serviced (i.e ., the interrupt vector, see section 16.1). the instruction in the interrupt table is typically a jmp instruction to the address o f the interrupt service routine (isr). the user can re-enable interrupts in the interrupt service routine by executing an ei instruct ion. interrupts can be nested to a level limited only by the available stack space. the program counter value, as well as the carry and zero flags (cf, zf), are stored onto the program stack by the automatic call instruction generated as part of the interrupt acknowledge process. the user firmware is responsible for ensuring that the processor state is preserved and restored during an interrupt. the push a instruction should typically be used as the first command in the isr to save the accumulator value and the pop a instruction should be used to restore the accumulator value 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w reserved i 2 c interrupt enable gpio/hapi interrupt enable dac interrupt enable reserved 1.024-ms interrupt enable 128- s interrupt enable usb bus rst interrupt enable figure 16-1. global interrupt enable register 0x20 (read/write) 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w reserved reserved reserved epb1 interrupt enable epb0 interrupt enable epa2 interrupt enable epa1 interrupt enable epa0 interrupt enable figure 16-2. usb endpoint interrupt enable register 0x21 (read/write)
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 27 of 48 just before the reti instruction. the program counter cf and zf are restored and interrupts are enabled when the reti instruction is executed. the di and ei instructions can be used to disable and enable interrupts, respectively. these instructions affect only the globa l interrupt enable bit of the cpu. if desired, ei can be used to re-enable interrupts while inside an isr, instead of waiting for the reti that exists the isr. while the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by examining the irq sense bit (bit 7 in the processor status and control register). 16.1 interrupt vectors the interrupt vectors supported by the usb controller are listed in table 16-1 . the lowest-numbered interrupt (usb bus reset interrupt) has the highest priority, and the highest-numbered interrupt (i 2 c interrupt) has the lowest priority. although reset is not an interrupt, the first instruction executed after a reset is at prom address 0x0000h ? which corresponds to the first entry in the interrupt vector table. because the jmp instruction is 2 bytes long, the interrupt vectors occupy 2 bytes. figure 16-3. interrupt controller functional diagram clr global interrupt interrupt acknowledge irqout usb reset clear interrupt interrupt priority encoder enable [0] d q 1 enable bit clr usb reset irq 128- s clr 128- s irq 1-ms clr 1-ms irq adda ep0 irq adda ep0 clr i 2 c irq vector enable [6] clk clr d q clk 1 i 2 c clr int i 2 c int usb adda ep1 irq adda ep1 clr irq sense irq controlled by di, ei, and reti instructions dac irq dac clr to cpu cpu reset gpio irq gpio clr adda ep2 irq adda ep2 clr adda ep3 irq adda ep3 clr adda ep4 irq adda ep4 clr (reg 0x20) (reg 0x20) clr enable [2] d q 1 clk int adda enp2 (reg 0x21) int enable sense
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 28 of 48 a pending address can be read from the interrupt vector register ( figure 16-4 ). the value read from this register is only valid if the global interrupt bit has been disabled, by executing the di instruction or in an interrupt service routine before interrupt s have been re-enabled. the value read from this register is the interrupt vector address; for example, a 0x06 indicates the 1 ms time r interrupt is the highest priority pending interrupt. 16.2 interrupt latency interrupt latency can be calculated from the following equation: interrupt latency = (number of clock cycles remaining in the current instruction) + (10 clock cycles for the call instruction) + (5 clock cycles for the jmp instruction) for example, if a 5 clock cycle instruction such as jc is being executed when an interrupt occurs, the first instruction of the interrupt service routine executes a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is issued. for a 12-mhz internal clock (6-mhz crystal), 20 clock periods is 20 / 12 mhz = 1.667 s. 16.3 usb bus reset interrupt the usb controller recognizes a usb reset when a single ended zero (se0) condition persists on the upstream usb port for 12 ? 16 s (the reset may be recognized for an se0 as short as 12 s, but is always recognized for an se0 longer than 16 s). se0 is defined as the condition in which both the d+ line and the d ? line are low. bit 5 of the status and control register is set to record this event. the interrupt is asserted at the end of the bus reset. if the usb reset occurs during the start-up delay following a por, the delay is aborted as described in section 7.1. the usb bus reset interrupt is generated when the se0 state is deasserted. a usb bus reset clears the following registers: sie section:usb device address registers (0x10, 0x40) table 16-1. interrupt vector assignments interrupt vector number rom address function not applicable 0x0000 execution after reset begins here 1 0x0002 usb bus reset interrupt 2 0x0004 128- s timer interrupt 3 0x0006 1.024-ms timer interrupt 4 0x0008 usb address a endpoint 0 interrupt 5 0x000a usb address a endpoint 1 interrupt 6 0x000c usb address a endpoint 2 interrupt 7 0x000e usb address a endpoint 3 interrupt 8 0x0010 usb address a endpoint 4 interrupt 9 0x0012 reserved 10 0x0014 dac interrupt 11 0x0016 gpio / hapi interrupt 12 0x0018 i 2 c interrupt 7 6 5 4 3 2 1 0 r r r r r reserved reserved reserved interrupt vector bit 4 interrupt vector bit 3 interrupt vector bit 2 interrupt vector bit 1 reads ? 0 ? figure 16-4. interrupt vector register 0x23 (read only)
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 29 of 48 16.4 timer interrupt there are two periodic timer interrupts: the 128- s interrupt and the 1.024-ms interrupt. the user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts first or the s uspend request first. 16.5 usb endpoint interrupts there are five usb endpoint interrupts, one per endpoint. a usb endpoint interrupt is generated after the usb host writes to a usb endpoint fifo or after the usb controller sends a packet to the usb host. the interrupt is generated on the last packet of the transaction (e.g., on the host ? s ack during an in, or on the device ack during on out). if no ack is received during an in transaction, no interrupt is generated. 16.6 dac interrupt each dac i/o pin can generate an interrupt, if enabled. the interrupt polarity for each dac i/o pin is programmable. a positive polarity is a rising edge input while a negative polarity is a falling edge input. all of the dac pins share a single interrupt vector, which means the firmware needs to read the dac port to determine which pin or pins caused an interrupt. if one dac pin has triggered an interrupt, no other dac pins can cause a dac interrupt until that pin has returned to its inact ive (non-trigger) state or the corresponding interrupt enable bit is cleared. the usb controller does not assign interrupt priority to different dac pins and the dac interrupt enable register is not cleared during the interrupt acknowledge process. 16.7 gpio/hapi interrupt each of the gpio pins can generate an interrupt, if enabled. the interrupt polarity can be programmed for each gpio port as part of the gpio configuration. all of the gpio pins share a single interrupt vector, which means the firmware needs to read th e gpio ports with enabled interrupts to determine which pin or pins caused an interrupt. a block diagram of the gpio interrupt logic is shown in figure 16-5 . refer to sections 9.1 and 9.2 for more information of setting gpio interrupt polarity and enabling individual gpio interrupts. if one port pin has triggered an interrupt, no other port pins can cause a gpio interrupt until that port pin has returned to i ts inactive (non-trigger) state or its corresponding port interrupt enable bit is cleared. the usb controller does not assign inte rrupt priority to different port pins and the port interrupt enable registers are not cleared during the interrupt acknowledge proces s. when hapi is enabled, the hapi logic takes over the interrupt vector and blocks any interrupt from the gpio bits, including ports/bits not being used by hapi. operation of the hapi interrupt is independent of the gpio specific bit interrupt enables, a nd is enabled or disabled only by bit 5 of the global interrupt enable register (0x20) when hapi is enabled. the settings of the gpio bit interrupt enables on ports/bits not used by hapi still effect the cmos mode operation of those ports/bits. the effect of figure 16-5. gpio interrupt structure port register or gate gpio interrupt flip flop clr gpio pin 1 = enable 0 = disable port interrupt enable register 1 = enable 0 = disable interrupt priority encoder irqout interrupt vector d q m u x 1 (1 input per gpio pin) global gpio interrupt enable (bit 5, register 0x20) ira configuration
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 30 of 48 modifying the interrupt bits while the port config bits are set to ? 10 ? is shown in table 9-1 . the events that generate hapi interrupts are described in section 14.0. 16.8 i 2 c interrupt the i 2 c interrupt occurs after various events on the i 2 c compatible bus to signal the need for firmware interaction. this generally involves reading the i 2 c status and control register ( figure 13-2 ) to determine the cause of the interrupt, loading/reading the i 2 c data register as appropriate, and finally writing the status and control register to initiate the subsequent transaction. the interrupt indicates that status bits are stable and it is safe to read and write the i 2 c registers. refer to section 13.0 for details on the i 2 c registers. when enabled, the i 2 c compatible state machines generate interrupts on completion of the following conditions. the referenced bits are in the i 2 c status and control register. 1. in slave receive mode, after the slave receives a byte of data. the addr bit is set if this is the first byte since a start o r restart signal was sent by the external master. firmware must read or write the data register as necessary, then set the ack, xmit mode, and continue bits appropriately for the next byte. 2. in slave receive mode, after a stop bit is detected. the received stop bit is set. if the stop bit follows a slave receive tr ansaction where the ack bit was cleared to 0, no stop bit detection occurs. 3. in slave transmit mode, after the slave transmits a byte of data. the ack bit indicates if the master that requested the byte acknowledged the byte. if more bytes are to be sent, firmware writes the next byte into the data register and then sets the xmit mode and continue bits as required. 4. in master transmit mode, after the master sends a byte of data. firmware should load the data register if necessary, and set the xmit mode, mstr mode, and continue/busy bits appropriately. clearing the mstr mode bit issues a stop signal to the i 2 c compatible bus and return to the idle state. 5. in master receive mode, after the master receives a byte of data. firmware should read the data and set the ack and continue/busy bits appropriately for the next byte. clearing the master bit at the same time causes the master state machine to issue a stop signal to the i 2 c compatible bus and leave the i 2 c compatible hardware in the idle state. 6. when the master loses arbitration. this condition clears the master bit and sets the arbitration lost bit immediately and the n waits for a stop signal on the i 2 c compatible bus to generate the interrupt. the continue/busy bit is cleared by hardware prior to interrupt conditions 1 to 4. once the data register has been read or writ ten, firmware should configure the other control bits and set the continue bit for subsequent transactions. following an interrupt from master mode, firmware should perform only one write to the status and control register that sets th e continue bit, without checking the value of the busy bit. the busy bit may otherwise be active and i 2 c register contents may be changed by the hardware during the transaction, until the i 2 c interrupt occurs. 17.0 usb overview the usb hardware consists of the logic for a full-speed usb port. the full-speed serial interface engine (sie) interfaces the microcontroller to the usb bus. an external series resistor (r ext ) must be placed in series with the d+ and d ? lines, as close to the corresponding pins as possible, to meet the usb driver requirements of the usb specifications. 17.1 usb serial interface engine (sie) the sie allows the cy7c64x13 microcontroller to communicate with the usb host. the sie simplifies the interface between the microcontroller and usb by incorporating hardware that handles the following usb bus activity independently of the microcon- troller: bit stuffing/unstuffing checksum generation/checking ack/nak/stall token type identification address checking firmware is required to handle the following usb interface tasks: coordinate enumeration by responding to setup packets fill and empty the fifos suspend/resume coordination verify and select data toggle values
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 31 of 48 17.2 usb enumeration the usb device is enumerated under firmware control. the following is a brief summary of the typical enumeration process of the cy7c64x13 by the usb host. for a detailed description of the enumeration process, refer to the usb specification. in this description, ? firmware ? refers to embedded firmware in the cy7c64x13 controller. 1. the host computer sends a setup packet followed by a data packet to usb address 0 requesting the device descriptor. 2. firmware decodes the request and retrieves its device descriptor from the program memory tables. 3. the host computer performs a control read sequence and firmware responds by sending the device descriptor over the usb bus, via the on-chip fifos. 4. after receiving the descriptor, the host sends a setup packet followed by a data packet to address 0 assigning a new usb address to the device. 5. firmware stores the new address in its usb device address register after the no-data control sequence completes. 6. the host sends a request for the device descriptor using the new usb address. 7. firmware decodes the request and retrieves the device descriptor from program memory tables. 8. the host performs a control read sequence and firmware responds by sending its device descriptor over the usb bus. 9. the host generates control reads from the device to request the configuration and report descriptors. 10.once the device receives a set configuration request, its functions may now be used. 17.3 usb upstream port status and control usb status and control is regulated by the usb status and control register, as shown in figure 17-1 . all bits in the register are cleared during reset. the three control bits allow the upstream port to be driven manually by firmware. for normal usb operation, all of these bits m ust be cleared. table 17-1 shows how the control bits affect the upstream port. table 17-1. control bit definition for upstream port bus activity (bit 3) is a ? sticky ? bit that indicates if any non-idle usb event has occurred on the upstream usb port. firmware should check and clear this bit periodically to detect any loss of bus activity. writing a ? 0 ? to the bus activity bit clears it, while writing a ? 1 ? preserves the current value. in other words, the firmware can clear the bus activity bit, but only the sie can set it. the upstream d ? and d+ (bits 4 and 5) are read only. these give the state of each upstream port pin individually: 1=high, 0=low. endpoint mode (bit 6) and endpoint size (bit 7) are used to configure the number and size of usb endpoints. see section 18.2 for a detailed description of these bits. 7 6 5 4 3 2 1 0 r/w r/w r r r/c r/w r/w r/w endpoint size endpoint mode d+ upstream d ? upstream bus activity control bit 2 control bit 1 control bit 0 figure 17-1. usb status and control register 0x1f (read/write) control bits control action 000 not forcing (sie controls driver) 001 force d+[0] high, d ? [0] low 010 force d+[0] low, d ? [0] high 011 force se0; d+[0] low, d ? [0] low 100 force d+[0] low, d ? [0] low 101 force d+[0] hiz, d ? [0] low 110 force d+[0] low, d ? [0] hiz 111 force d+[0] hiz, d ? [0] hiz
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 32 of 48 18.0 usb serial interface engine operation usb device address a includes up to five endpoints: epa0, epa1, epa2, epa3, and epa4. endpoint (epa0) allows the usb host to recognize, set-up, and control the device. in particular, epa0 is used to receive and transmit control (including set-u p) packets. 18.1 usb device address the usb controller provides one usb device address with five endpoints. the usb device address register contents are cleared during a reset, setting the usb device address to zero and marking this address as disabled. figure 18-1 shows the format of the usb address registers. bit 7 (device address enable) in the usb device address register must be set by firmware before the sie can respond to usb traffic to this address. the device addresses in bits [6:0] are set by firmware during the usb enumeration process to the non-z ero address assigned by the usb host. 18.2 usb device endpoints the cy7c64x13 controller supports one usb device address and five endpoints for communication with the host. the configu- ration of these endpoints, and associated fifos, is controlled by bits [7,6] of the usb status and control register (0x1f). bit 7 controls the size of the endpoints and bit 6 controls the number of endpoints. these configuration options are detailed in table 18-1 . the ? unused ? fifo areas in the following table can be used by the firmware as additional user ram space. when the sie writes data to a fifo, the internal data bus is driven by the sie; not the cpu. this causes a short delay in the cpu operation. the delay is three clock cycles per byte. for example, an 8-byte data write by the sie to the fifo generates a delay of 2 s (3 cycles/byte * 83.33 ns/cycle * 8 bytes). 18.3 usb control endpoint mode register all usb devices are required to have a control endpoint 0 (epa0) that is used to initialize and control each usb address. endpo int 0 provides access to the device configuration information and allows generic usb status and control accesses. endpoint 0 is bidirectional to both receive and transmit data. the other endpoints are unidirectional, but selectable by the user as in or ou t endpoints. the endpoint mode register is cleared during reset. the endpoint zero epa0 mode register uses the format shown in figure 18-2 . 7 6 5 4 3 2 1 0 device address enable device address bit 6 device address bit 5 device address bit 4 device address bit 3 device address bit 2 device address bit 1 device address bit 0 figure 18-1. usb device address register 0x10 (read/write) table 18-1. memory allocation for endpoints i/o status [7,6] [0,0] [1,0] [0,1] [1,1] label start address size label start address size label start address size label start address size unused 0xd8 8 unused 0xa8 8 epa4 0xd8 8 epa4 0xb0 8 unused 0xe0 8 unused 0xb0 8 epa3 0xe0 8 epa3 0xa8 8 epa2 0xe8 8 epa0 0xb8 8 epa2 0xe8 8 epa0 0xb8 8 epa1 0xf0 8 epa1 0xc0 32 epa1 0xf0 8 epa1 0xc0 32 epa0 0xf8 8 epa2 0xe0 32 epa0 0xf8 8 epa2 0xe0 32 7 6 5 4 3 2 1 0 endpoint 0 setup received endpoint 0 in received endpoint 0 out received ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 figure 18-2. usb device endpoint zero mode register 0x12 (read/write)
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 33 of 48 bits[7:5] in the endpoint 0 mode registers are status bits that are set by the sie to report the type of token that was most re cently received by the corresponding device address. these bits must be cleared by firmware as part of the usb processing. the ack bit (bit 4) is set whenever the sie engages in a transaction to the register ? s endpoint that completes with an ack packet. the setup pid status (bit 7) is forced high from the start of the data packet phase of the setup transaction until the start of the ack packet returned by the sie. the cpu is prevented from clearing this bit during this interval, and subsequently, until t he cpu first does an iord to this endpoint 0 mode register. bits[6:0] of the endpoint 0 mode register are locked from cpu write operations whenever the sie has updated one of these bits, which the sie does only at the end of the token phase of a transaction (setup... data... ack, out... data... ack, or in... data ... ack). the cpu can unlock these bits by doing a subsequent read of this register. only endpoint 0 mode registers are locked when updated. the locking mechanism does not apply to the mode registers of other endpoints. because of these hardware locking features, firmware must perform an iord after an iowr to an endpoint 0 register. this verifie s that the contents have changed as desired, and that the sie has not updated these values. while the setup bit is set, the cpu cannot write to the endpoint zero fifos. this prevents firmware from overwriting an incomin g setup transaction before firmware has a chance to read the setup data. refer to table 18-1 for the appropriate endpoint zero memory locations. the mode bits (bits [3:0]) control how the endpoint responds to usb bus traffic. the mode bit encoding is shown in table 19-1 . additional information on the mode bits can be found in table 19-2 and table 19-3 . note that the sie offers an ? ack out - status in ? mode and not an ? ack out - nak in ? mode. therefore, if following the status stage of a control write transfer a usb host were to immediately start the next transfer, the new setup packet could override the data payload of the data stage of the previous control write. 18.4 usb non-control endpoint mode registers the format of the non-control endpoint mode register is shown in figure 18-3 . the mode bits (bits [3:0]) of the endpoint mode register control how the endpoint responds to usb bus traffic. the mode bit encoding is shown in table 19-1 . the ack bit (bit 4) is set whenever the sie engages in a transaction to the register ? s endpoint that completes with an ack packet. if stall (bit 7) is set, the sie stalls an out packet if the mode bits are set to ack-in, and the sie stalls an in packet if th e mode bits are set to ack-out. for all other modes, the stall bit must be a low. bits 5 and 6 are reserved and must be written to zero during register writes. 18.5 usb endpoint counter registers there are five endpoint counter registers, with identical formats for both control and non-control endpoints. these registers contain byte count information for usb transactions, as well as bits for data packet status. the format of these registers is s hown in figure 18-4 : the counter bits (bits [5:0]) indicate the number of data bytes in a transaction. for in transactions, firmware loads the count with the number of bytes to be transmitted to the host from the endpoint fifo. valid values are 0 to 32, inclusive. for out or setup transactions, the count is updated by hardware to the number of data bytes received, plus 2 for the crc bytes. valid values are 2 to 34, inclusive. data valid bit 6 is used for out and setup tokens only. data is loaded into the fifos during the transaction, and then the data valid bit is set if a proper crc is received. if the crc is not correct, the endpoint interrupt occurs, but data valid is clear ed to a zero. data 0/1 toggle bit 7 selects the data packet ? s toggle state: 0 for data0, 1 for data1. for in transactions, firmware must set this bit to the desired state. for out or setup transactions, the hardware sets this bit to the state of the received data togg le bit. 7 6 5 4 3 2 1 0 stall reserved reserved ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 figure 18-3. usb non-control device endpoint mode registers 0x14, 0x16, 0x42, 0x44, (read/write) 7 6 5 4 3 2 1 0 data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 figure 18-4. usb endpoint counter registers 0x11, 0x13, 0x15, 0x41, 0x43 (read/write)
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 34 of 48 whenever the count updates from a setup or out transaction on endpoint 0, the counter register locks and cannot be written by the cpu. reading the register unlocks it. this prevents firmware from overwriting a status update on incoming setup or out transactions before firmware has a chance to read the data. only endpoint 0 counter register is locked when updated. the lockin g mechanism does not apply to the count registers of other endpoints. 18.6 endpoint mode/count registers update and locking mechanism the contents of the endpoint mode and counter registers are updated, based on the packet flow diagram in figure 18-5 . two time points, update and setup, are shown in the same figure. the following activities occur at each time point: update: 1. endpoint mode register - all the bits are updated (except the setup bit of the endpoint 0 mode register). 2. counter registers - all bits are updated. 3. interrupt - if an interrupt is to be generated as a result of the transaction, the interrupt flag for the corresponding endpo int is set at this time. for details on what conditions are required to generate an endpoint interrupt, refer to table 19-2 . 4. the contents of the updated endpoint 0 mode and counter registers are locked, except the setup bit of the endpoint 0 mode register which was locked earlier. setup: the setup bit of the endpoint 0 mode register is forced high at this time. this bit is forced high by the sie until the end of the data phase of a control write transfer. the setup bit can not be cleared by firmware during this time. the affected mode and counter registers of endpoint 0 are locked from any cpu writes once they are updated. these registers can be unlocked by a cpu read, only if the read operation occurs after the update. the firmware needs to perform a register read as a part of the endpoint isr processing to unlock the effected registers. the locking mechanism on mode and counter registers ensures that the firmware recognizes the changes that the sie might have made since the previous io read of that register.
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 35 of 48 figure 18-5. token/data packet flow diagram 1. in token h o s t d e v i c e token packet s y n c i n a d d r e n d p c r c 5 data packet s y n c d a t a 1 c r c 1 6 data h/s pkt token packet s y n c i n a d d r e n d p c r c 5 s y n c a c k h/s pkt s y n c nak/ stall update 2. out or setup token without crc error token packet s y n c o u t a d d r e n d p c r c 5 data packet s y n c d a t a 1 c r c 1 6 data set up h/s pkt s y n c ack, nak, stall 3. out or setup token with crc error token packet s y n c o u t a d d r e n d p c r c 5 set up data packet s y n c d a t a 1 c r c 1 6 data update only if fifo is written (see table 20-3) update a) b) update setup update only if fifo is written (see table 19-3 )
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 36 of 48 19.0 usb mode tables the ? in ? column represents the sie ? s response to the token type. a disabled endpoint remains disabled until it is changed by firmware, and all endpoints reset to the disabled state. any setup packet to an enabled endpoint with mode set to accept setups is changed by the sie to 0001 (naking). any mode set to accept a setup, acks a valid setup transaction. most modes that control transactions involving an ending ack, are changed by the sie to a corresponding mode which naks subsequent packets following the ack. exceptions are modes 1010 and 1110. a control endpoint has three extra status bits for pid (setup, in and out), but must be placed in the correct mode to function as such. non-control endpoints should not be placed into modes that accept setups. a ? check ? on an out token during a status transaction checks to see that the out is of zero length and has a data toggle (dtog) of ? 1 ? . if the dtog bit is set and the received out packet has zero length, the out is acked to complete the transaction. otherwise, the out is stalled. note: 3. stall bit is bit 7 of the usb non-control device endpoint mode registers. for more information, refer to section 18.4. table 19-1. usb register mode encoding mode encoding setup in out comments disable 0000 ignore ignore ignore ignore all usb traffic to this endpoint nak in/out 0001 accept nak nak forced from set-up on control endpoint, from modes other than 0000 status out only 0010 accept stall check for control endpoints stall in/out 0011 accept stall stall for control endpoints ignore in/out 0100 accept ignore ignore for control endpoints isochronous out 0101 ignore ignore always for isochronous endpoints status in only 0110 accept tx 0 stall for control endpoints isochronous in 0111 ignore tx cnt ignore for isochronous endpoints nak out 1000 ignore ignore nak an ack from mode 1001 --> 1000 ack out (stall [3] =0) ack out (stall [3] =1) 1001 1001 ignore ignore ignore ignore ack stall this mode is changed by sie on issuance of ack --> 1000 nak out - status in 1010 accept tx 0 nak an ack from mode 1011 --> 1010 ack out - status in 1011 accept tx 0 ack this mode is changed by sie on issuance of ack --> 1010 nak in 1100 ignore nak ignore an ack from mode 1101 --> 1100 ack in (stall [3] =0) ack in( stall [3] =1) 1101 1101 ignore ignore tx cnt stall ignore ignore this mode is changed by sie on issuance of ack --> 1100 nak in - status out 1110 accept nak check an ack from mode 1111 --> 111 ack in - status out ack in - status out 1111 accept tx cnt check this mode is changed by sie on issuance of ack -->1110
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 37 of 48 the response of the sie can be summarized as follows: 1. the sie only responds to valid transactions and ignores non-valid ones. 2. the sie generates an interrupt when a valid transaction is completed or when the fifo is corrupted. fifo corruption occurs during an out or setup transaction to a valid internal address that ends with a non-valid crc. 3. an incoming data packet is valid if the count is < endpoint size + 2 (includes crc) and passes all error checking. 4. an in is ignored by an out configured endpoint and vice versa. 5. the in and out pid status is updated at the end of a transaction. 6. the setup pid status is updated at the beginning of the data packet phase. 7. the entire endpoint 0 mode register and the count register are locked from cpu writes at the end of any transaction to that endpoint in which either an ack is transferred or the mode bits have changed. these registers are only unlocked by a cpu read of these registers, and only if that read happens after the transaction completes. this represents about a 1- s window in which the cpu is locked from register writes to these usb registers. normally, the firmware should perform a register read at the beginning of the endpoint isrs to unlock and get the mode register information. the interlock on the mode and count registers ensures that the firmware recognizes the changes that the sie might have made during the previous transaction. table 19-2. decode table for table 19-3 : ? details of modes for differing traffic conditions ? properties of incoming packet encoding status bits what the sie does to mode bits pid status bits interrupt? end point mode end point mode 3 2 1 0 token count buffer dval dtog dval count setup in out ack 3 2 1 0 response int setup in out the validity of the received data the quality status of the dma buffer the number of received bytes acknowledge phase completed legend: uc: unchanged tx: transmit tx0: transmit 0-length packet x: don ? t care rx: receive available for control endpoint only
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 38 of 48 table 19-3. details of modes for differing traffic conditions (see table 19-2 for the decode legend) end point mode pid set end point mode 3 2 1 0 token count buffer dval dtog dval count setup in out ack 3 2 1 0 response int setup packet (if accepting) see table 19-1 setup <= 10 data valid updates 1 updates 1 uc uc 1 0 0 0 1 ack yes see table 19-1 setup > 10 junk x updates updates updates 1 uc uc uc nochange ignore yes see table 19-1 setup x junk invalid updates 0 updates 1 uc uc uc nochange ignore yes disabled 0 0 0 0 x x uc x uc uc uc uc uc uc uc nochange ignore no nak in/out 0 0 0 1 out x uc x uc uc uc uc uc 1 uc nochange nak yes 0 0 0 1 in x uc x uc uc uc uc 1 uc uc nochange nak yes ignore in/out 0 1 0 0 out x uc x uc uc uc uc uc uc uc nochange ignore no 0 1 0 0 in x uc x uc uc uc uc uc uc uc nochange ignore no stall in/out 0 0 1 1 out x uc x uc uc uc uc uc 1 uc nochange stall yes 0 0 1 1 in x uc x uc uc uc uc 1 uc uc nochange stall yes control write normal out/premature status in 1 0 1 1 out <= 10 data valid updates 1 updates uc uc 1 1 1 0 1 0 ack yes 1 0 1 1 out > 10 junk x updates updates updates uc uc 1 uc nochange ignore yes 1 0 1 1 out x junk invalid updates 0 updates uc uc 1 uc nochange ignore yes 1 0 1 1 in x uc x uc uc uc uc 1 uc 1 nochange tx 0 yes nak out/premature status in 1 0 1 0 out <= 10 uc valid uc uc uc uc uc 1 uc nochange nak yes 1 0 1 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 1 0 1 0 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 1 0 1 0 in x uc x uc uc uc uc 1 uc 1 nochange tx 0 yes status in/extra out 0 1 1 0 out <= 10 uc valid uc uc uc uc uc 1 uc 0 0 1 1 stall yes 0 1 1 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 0 1 1 0 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 0 1 1 0 in x uc x uc uc uc uc 1 uc 1 nochange tx 0 yes control read normal in/premature status out 1 1 1 1 out 2 uc valid 1 1 updates uc uc 1 1 nochange ack yes 1 1 1 1 out 2 uc valid 0 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 1 out !=2 uc valid updates 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 1 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 1 1 1 1 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 1 1 1 1 in x uc x uc uc uc uc 1 uc 1 1 1 1 0 ack (back) yes nak in/premature status out 1 1 1 0 out 2 uc valid 1 1 updates uc uc 1 1 nochange ack yes 1 1 1 0 out 2 uc valid 0 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 0 out !=2 uc valid updates 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 1 1 1 0 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 1 1 1 0 in x uc x uc uc uc uc 1 uc uc nochange nak yes status out/extra in 0 0 1 0 out 2 uc valid 1 1 updates uc uc 1 1 nochange ack yes 0 0 1 0 out 2 uc valid 0 1 updates uc uc 1 uc 0 0 1 1 stall yes 0 0 1 0 out !=2 uc valid updates 1 updates uc uc 1 uc 0 0 1 1 stall yes
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 39 of 48 end point mode pid set end point mode 3 2 1 0 token count buffer dval dtog dval count setup in out ack 3 2 1 0 response int 0 0 1 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 0 0 1 0 out x uc invalid uc uc uc uc 1 uc uc nochange ignore no 0 0 1 0 in x uc x uc uc uc uc 1 uc uc 0 0 1 1 stall yes out endpoint normal out/erroneous in 1 0 0 1 out <= 10 data valid updates 1 updates uc uc 1 1 1 0 0 0 ack yes 1 0 0 1 out > 10 junk x updates updates updates uc uc 1 uc nochange ignore yes 1 0 0 1 out x junk invalid updates 0 updates uc uc 1 uc nochange ignore yes 1 0 0 1 in x uc x uc uc uc uc uc uc uc nochange ignore no (stall [3] = 0) 1 0 0 1 in x uc x uc uc uc uc uc uc uc nochange stall no (stall [3] = 1) nak out/erroneous in 1 0 0 0 out <= 10 uc valid uc uc uc uc uc 1 uc nochange nak yes 1 0 0 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 1 0 0 0 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 1 0 0 0 in x uc x uc uc uc uc uc uc uc nochange ignore no isochronous endpoint (out) 0 1 0 1 out x updates updates updates updates updates uc uc 1 1 nochange rx yes 0 1 0 1 in x uc x uc uc uc uc uc uc uc nochange ignore no in endpoint normal in/erroneous out 1 1 0 1 out x uc x uc uc uc uc uc uc uc nochange ignore no (stall [3] = 0) 1 1 0 1 out x uc x uc uc uc uc uc uc uc nochange stall no (stall [3] = 1) 1 1 0 1 in x uc x uc uc uc uc 1 uc 1 1 1 0 0 ack (back) yes nak in/erroneous out 1 1 0 0 out x uc x uc uc uc uc uc uc uc nochange ignore no 1 1 0 0 in x uc x uc uc uc uc 1 uc uc nochange nak yes isochronous endpoint (in) 0 1 1 1 out x uc x uc uc uc uc uc uc uc nochange ignore no 0 1 1 1 in x uc x uc uc uc uc 1 uc uc nochange tx yes table 19-3. details of modes for differing traffic conditions (see table 19-2 for the decode legend) (continued)
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 40 of 48 20.0 sample schematic xtalo xtali d0- d0+ vcc vref vpp gnd gnd in gnd out usb-b vbus d- d+ gnd .01 uf 6.000 mhz 22x2(r ext ) 0v 0v 0v vbus vref vref 0v .01 uf 0v 2.2 uf 2.2 uf 1.5k shell 10m 4.7 nf 250vac optional 3.3v regulator (r uup )
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 41 of 48 21.0 absolute maximum ratings storage temperature ........................................................................................................... ............................... ? 65 c to +150 c ambient temperature with power applied ......................................................................................... ........................0 c to +70 c supply voltage on v cc relative to v ss .................................................................................................................... ? 0.5v to +7.0v dc input voltage............................................................................................................... ............................ ? 0.5v to +v cc +0.5v dc voltage applied to outputs in high z state .................................................................................. .......... ? 0.5v to +v cc +0.5v power dissipation .............................................................................................................. ................................................500 mw static discharge voltage ...................................................................................................... ............................................. >2000v latch-up current .............................................................................................................. .............................................. >200 ma max output sink current into port 0, 1, 2, 3, and dac[1:0] pins ............................................................... ....................... 60 ma max output sink current into dac[7:2] pins ..................................................................................... ................................. 10 ma 22.0 electrical characteristics f osc = 6 mhz; operating temperature = 0 to 70 c, v cc = 4.0v to 5.25v parameter conditions min. max. unit general v ref reference voltage 3.3v 5% 3.15 3.45 v v pp programming voltage (disabled) ? 0.4 0.4 v i cc v cc operating current no gpio source current 50 ma i sb1 supply current ? suspend mode 50 a i ref v ref operating current note 5 30 ma i il input leakage current any pin 1 a usb interface v di differential input sensitivity | (d+) ? (d ? ) | 0.2 v v cm differential input common mode range 0.8 2.5 v v se single ended receiver threshold 0.8 2.0 v c in transceiver capacitance 20 pf i lo hi-z state data line leakage 0 v < v in < 3.3 v ? 10 10 a r ext external usb series resistor in series with each usb pin 19 21 ? r uup external upstream usb pull-up resistor 1.5 k ? 5%, d+ to v reg 1.425 1.575 k ? power on reset t vccs v cc ramp rate linear ramp 0v to v cc [4] 0100ms usb upstream v uoh static output high 15 k ? 5% to gnd 2.8 3.6 v v uol static output low 1.5 k ? 5% to v ref 0.3 v z o usb driver output impedance including r ext resistor 28 44 ? general purpose i/o (gpio) r up pull-up resistance (typical 14 k ?) 8.0 24.0 k ? v ith input threshold voltage all ports, low to high edge 20% 40% v cc v h input hysteresis voltage all ports, high to low edge 2% 8% v cc v ol port 0,1,2,3 output low voltage i ol = 3 ma i ol = 8 ma 0.4 2.0 v v v oh output high voltage i oh = 1.9 ma (all ports 0,1,2,3) 2.4 v notes: 4. power-on reset occurs whenever the voltage on v cc is below approximately 2.5v. 5. this is based on transitions every 2 full-speed bit times on average.
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 42 of 48 notes: 6. irange: i sinkn (15)/ i sinkn (0) for the same pin. 7. t ratio = i sink1 [1:0](n)/i sink0 [7:2](n) for the same n, programmed. 8. i lin measured as largest step size vs. nominal according to measured full scale and zero programmed values. dac interface r up dac pull-up resistance (typical 14 k ?) 8.0 24.0 k ? i sink0(0) dac[7:2] sink current (0) v out = 2.0v dc 0.1 0.3 ma i sink0(f) dac[7:2] sink current (f) v out = 2.0v dc 0.5 1.5 ma i sink1(0) dac[1:0] sink current (0) v out = 2.0v dc 1.6 4.8 ma i sink1(f) dac[1:0] sink current (f) v out = 2.0v dc 8 24 ma i range programmed isink ratio: max/min v out = 2.0v dc [6] 46 t ratio tracking ratio dac[1:0] to dac[7:2] v out = 2.0v [7] 14 22 i sinkdac dac sink current v out = 2.0v dc 1.6 4.8 ma i lin differential nonlinearity dac port [8] 0.6 lsb parameter conditions min. max. unit
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 43 of 48 notes: 9. per table 7-6 of revision 1.1 of usb specification. 10. for 25-pf load. 11. assumes chip select cs is asserted (low). 23.0 switching characteristics (f osc = 6.0 mhz) parameter description min. max. unit clock source f osc clock rate 6 0.25% mhz t cyc clock period 166.25 167.08 ns t ch clock high time 0.45 t cyc ns t cl clock low time 0.45 t cyc ns usb full speed signaling [9] t rfs transition rise time 4 20 ns t ffs transition fall time 4 20 ns t rfmfs rise / fall time matching; (t r /t f ) 90 111 % t dratefs full speed date rate 12 0.25% mb/s dac interface t sink current sink response time 0.8 s hapi read cycle timing t rd read pulse width 15 ns t oed oe low to data valid [10, 11] 40 ns t oez oe high to data high-z [11] 20 ns t oedr oe low to data_ready deasserted [10, 11] 0 60 ns hapi write cycle timing t wr write strobe width 15 ns t dstb data valid to stb high (data set-up time) [11] 5 ns t stbz stb high to data high-z (data hold time) [11] 15 ns t stble stb low to latch_empty deasserted [10, 11] 0 50 ns timer signals t watch watch dog timer period 8.192 14.336 ms
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 44 of 48 figure 23-1. clock timing figure 23-2. usb data signal timing figure 23-3. hapi read by external interface from usb microcontroller clock t cyc t cl t ch 90% 10% 90% 10% d ? d + t r t r oe (p2.5, input) data (output) stb (p2.4, input) dreadypin (p2.3, output) internal write internal addr port0 d[23:0] t oed t oez t rd t oedr cs (p2.6, input) int (shown for drdy polarity=0) interrupt generated (ready)
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 45 of 48 figure 23-4. hapi write by external device to usb microcontroller data (input) lemptypin (p2.2, output) internal read internal addr port0 d[23:0] t stble t wr t stbz t dstb oe (p2.5, input) cs (p2.6, input) stb (p2.4, input) (not empty) (shown for lempty polarity=0) int interrupt generated
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 46 of 48 24.0 ordering information ordering code prom size package name package type operating range cy7c64013-sc 8 kb s21 28-pin (300-mil) soic commercial cy7c64013-pc 8 kb p21 28-pin (300-mil) pdip commercial CY7C64113-PVC 8 kb o48 48-pin (300-mil) ssop commercial 25.0 package diagrams 48-lead shrunk small outline package o48 51-85061-b 51-85014-b 28-lead (300-mil) molded dip p21
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 47 of 48 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. 25.0 package diagrams (continued) 28-lead (300-mil) molded soic s21 51-85026-a
cy7c64013 cy7c64113 document #: 38-08001 rev. ** page 48 of 48 document title: cy7c64013, cy7c64113 full-speed usb (12 mbps) function document number: 38-08001 rev. ecn no. issue date orig. of change description of change ** 109962 12/16/01 szv change from spec number: 38-00626 to 38-08001

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